Seongwon (Gabriel) Yoon

I am a Ph.D. student in Electrical and Computer Engineering at Georgia Tech, advised by Prof. Shimeng Yu in the Laboratory for Emerging Devices and Circuits. My research focuses on optical switch and interconnect co-design with silicon photonics for scalable AI systems.

I received my B.S. in Materials Science and Engineering from Seoul National University, Summa Cum Laude.

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Research Interests

My research focuses on silicon photonics and optical interconnects for AI infrastructure. I study how photonic integrated circuits (PICs) can replace copper across the scale-up and scale-out hierarchy of AI clusters, including co-packaged optics (CPO), near-packaged optics, and wafer-scale optical interconnects.

On the system side, I work on optical link modeling and cross-layer analysis of power, thermal tuning overhead, and performance for large-scale LLM training. On the device side, I explore CMOS-compatible emerging devices such as ferroelectrics and oxide transistors for photonic–electronic integration, along with modulator and transceiver device physics.

Keywords: Silicon Photonics, Optical Interconnects, Optical Device Modeling, AI Infrastructure

Publications
Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation
Seongwon Yoon, Pin-Jun Chen, Shimeng Yu
arXiv preprint arXiv:2608.24637, 2026.

Cross-layer analysis of wafer-scale optical interconnects for MoE training. Thermo-optic ring tuning stalls inflate iteration time by 1.6–2.8×; an athermal ferroelectric ring with a programmable setpoint recovers near-ideal fat-tree performance.

CMOS+X: Stacking Memories based on Oxide Transistors upon GPGPU Platforms
Faaiq Waqar, Ming-Yen Lee, Seongwon Yoon, Seongkwang Lim, Shimeng Yu
Proceedings of the International Symposium on Memory Systems (MEMSYS), pp. 64–77, 2025.

BEOL-compatible amorphous oxide semiconductor (W-doped In2O3) gain-cell memories stacked monolithically above GPGPU logic. AOS 1T1C L2 caches deliver up to 5.1× performance per watt and 6.1× memory density over an HD-SRAM baseline.

A CMOS Image Sensor Pixel Readout Circuit Design Using Back-End-of-Line (BEOL)-Compatible Oxide Transistors
Seongwon Yoon, Janak Sharda, Omkar Phadke, Shimeng Yu
IEEE 68th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1026–1030, 2025.

Pixel readout circuit for a 2-wafer stacked CMOS image sensor with the readout placed in the BEOL using oxide transistors, removing the need for a third readout wafer. Best Paper Award.

Solving Max-Cut Problem Using Spiking Boltzmann Machine Based on Neuromorphic Hardware with Phase Change Memory
Yu Gyeong Kang, Masatoshi Ishii, Jaeweon Park, Uicheol Shin, Suyeon Jang, Seongwon Yoon, Mingi Kim, Atsuya Okazaki, Megumi Ito, Akiyo Nomura, Kohji Hosokawa, Matthew BrightSky, Sangbum Kim
Advanced Science, vol. 11, no. 46, 2406433, 2024.

Max-Cut problem solver using the IBM neuromorphic chip (phase-change material GST based non-volatile memory synapse) hardware-aware simulator.

Clinical Validity and Precision of Deep Learning-Based Cone-Beam Computed Tomography Automatic Landmarking Algorithm
Jungeun Park, Seongwon Yoon, Hannah Kim, Youngjun Kim, Uilyong Lee, Hyungseog Yu
Imaging Science in Dentistry, vol. 54, no. 3, pp. 240–250, 2024.

Evaluated the clinical validity and accuracy of a deep learning-based CBCT automatic landmarking algorithm by comparing 3D head measurements from manual and automatic landmarking. This study further developed into the business solution CT Landmark Detection.

Solving Constraint Satisfaction Problem with Spiking Neural Network based on 1.4M 6T2R PCM Synaptic Array with 1.6K Stochastic LIF Neurons Neuromorphic Hardware
Seongwon Yoon, Uicheol Shin, Sangbum Kim
The 28th Korean Conference on Semiconductors (KCS), 2021.

Traveling Salesman Problem (TSP) solver based on the IBM neuromorphic chip (phase-change material GST based non-volatile memory synapse) hardware-aware simulator.

Chip Tapeout
RRAM-Integrated CMOS Image Sensor Pixel Readout Chip
180 nm CMOS, 3-metal MPW through the National NanoFab Center (NNFC), Korea
Laboratory for Emerging Devices and Circuits, Georgia Tech, 2025.

Talks
Optical Interconnect for LLM, MoE and Agentic AI
Future of CMOS and Talent Workshop, Session 2: Memory Wall and Interconnect Wall
Georgia Tech Global Learning Center, Atlanta, GA, March 26, 2026.

[slides] [workshop agenda]

Skills

Photonic & Electromagnetic Simulation: Ansys Lumerical (FDTD, MODE, INTERCONNECT)

Device & Multiphysics Simulation: TCAD, Ansys Mechanical (thermal and structural analysis)

Scientific Computing: MATLAB

Graduate Coursework

Courses taken at Georgia Tech.

Networking

  • ECE 8803 Photonics for AI
  • CS 7260 Internetworking Architectures and Protocols
  • ECE 6607 Computer Communication Networks
  • ECE 6612 Computer Network Security

VLSI & Semiconductor Devices

  • ECE 6133 Physical Design Automation of VLSI Systems
  • ECE 6465 Memory Device Technologies and Applications
  • ECE 8803 Advanced Logic Transistors

Computer Architecture & ML Systems

  • ECE 6100 Advanced Computer Architecture
  • ECE 8803 Hardware-Software Co-Design for Machine Learning Systems

Machine Learning & AI

  • CS 7750 Mathematical Foundations of Machine Learning
  • ECE 8803 Generative and Geometric Deep Learning

Design and source code from Jon Barron Website.